Traditional data switches would gather all input signals into a single, centralized switching engine, or a few scattered switching engines. Each switching engine would accept traffic for those outputs it services. The bandwidth of the switching engines is limited. This limits the port capacities to at most several hundred to a few thousand ports of 10 Giga bits per second each. As such, when the capacity of a data center exceeds the ability of such a switch to handle all of its traffic, multiple switches are needed to handle the traffic demands of the data center. As traffic entering the data center on one switch may have to exit on another data switch, a multiplicity of ports on each switch are dedicated to interconnecting the switches together. This consumes expensive resources and makes switching more expensive per data packet for data centers that are too large for one data switch.
A particular known switching architecture is the shared bus architecture. It is used extensively in the industry today, for example, in the Cisco® Catalyst® 6500 family of data switches. The shared bus architecture has been in use for over twenty years. Data switches based on the PCI bus, which is a form of a shared bus architecture, have been around since close to the inception of the PCI bus in 1993. In the shared bus architecture, all incoming data traffic is presented to a common data bus where all outgoing ports may accept a data packet placed on this shared bus. Incoming data traffic ports will arbitrate with each other for access to the shared bus. Once granted access, the incoming data packet will be placed on the bus and the outgoing port or ports that are to accept the traffic are notified that they are to do so. The limitations of the shared bus architecture are several. At most, one data packet can be transferred in a predefined period of time, limiting the number of packets that can pass through the shared bus architecture in one second. State of the art of technology precludes being able to transfer data packets more frequently than what the technology can handle. As technology improves, the predefined periods of time can be made smaller, allowing more packets to pass through the shared bus over the same one second period of time. However, improvements in technology are not able to keep pace with the rate of increase in network traffic. Another limitation of the shared bus architecture is that all data packets must pass through it, limiting the size and scope of any data switch built around it, as they have to be physically close to the actual implementation of the shared bus architecture.
A method of getting around the limitations of the shared bus architecture is the use of a multi-node bus, each with their own internal switching capability. The Advanced Switching Interconnect (ASI) is an architecture that uses multiple switching nodes connected to multiple data sources and data destinations. ASI passes data packets from a data source to a data destination by advancing the data packet from switching node to switching node, using information in the header of the data packet to determine which outgoing port on each node an incoming packet must go to. ASI uses physical addresses when a packet advances from node to node. Multiple packets may concurrently pass through the ASI architecture. However, ASI uses a relative address, not an absolute address. ASI's claim to fame is its ability to go in both directions when a packet traverses across a network made of ASI switching engines. It does so by entering an ASI switching engine on a port, and through the use of a header value, will count in a clockwise direction by the indicated number of ports over to exit the ASI switching node. It then advances the header value by the number of bits needed to count ports and get through each ASI switching node. At the destination, the packet is analyzed, and a new packet is generated utilizing the same header but with the direction bit changed. When going in the reverse direction the header value counts backwards, and as a packet enters each ASI switching node, it counts ports in a counter-clockwise direction until it reaches the original packet source. ASI lacks many features needed for high capacity switching, however. It does not have redundancy built into it, it does not have queuing (that is, the ability to pass higher priority packets before passing lower priority packets), packet duplication, or the buffering needed for data to enter and leave on all ports concurrently under all combinations of inputs and outputs. Further, ASI requires that the source and destination processors understand the ASI network when passing data packets through it. To qualify for a network data switch, the architecture of the data switch must be transparent to the end users. To qualify as a layer 2 data switch all the end user needs to do is provide a logical address of its destination and let the switch and the network the switch is in figure out how to route the data packet.